In the integrated circuits, a great number of devices and circuits are fabricated on a single chips. Various kinds of devices like transistors, resistors, and capacitors are formed together. Each device must operate independently without interfering each other, especially under the higher and higher packing density of the integrated circuits. An isolation region is formed on the semiconductor substrate for separating different devices or different functional regions. The isolation region is generally a non-active and insulated region for isolating between devices, wells for transistors, and functional regions.
LOCOS (local oxidation of silicon) is a widely applied technology in forming the isolation region. The isolation regions are created by oxidizing the portion of the silicon substrate between each active devices and functional regions. The LOCOS technology provide the isolation region with a simple manufacturing process and low cost, especially when compared with other trench isolation processes. However, with the fabrication of semiconductor integrated circuits becomes densely packed, the application of the LOCOS technology is quite limited. For a highly packed circuits like the circuits with devices of deep sub-micrometer feature sizes, the LOCOS process has several challenges in fulfilling the isolating specifications.
The trench isolation process, or the shallow trench isolation (STI) process, is another isolation process proposed especially for semiconductor chips with high integration. A trench region is formed in the semiconductor with a depth deep enough for isolating the devices or different wells. In general, a trench is etched and refilled with insulating materials in the trench isolation process. The refilled trench regions are developed for the application in the VLSI and ULSI level. In addition, capacitors can also be formed within the trench by filling both insulating and conductive materials sequentially for the application of forming memory cells.
The conventional LOCOS isolation process suffers the problems like large bird's beak, local field oxide thinning effect, and stress-induced silicon defects. In the article of "Characteristics of CMOS Device Isolation for the ULSI Age" by A. Bryant et al. (in IEDM Tech. Dig., p. 671, 1994), different isolation processes are investigated. They reviewed how LOCOS and STI isolation are being improved to meet the scaling requirements. The scalability of LOCOS for sub-half-micrometer CMOS technologies is a widely identified question. The issues like lateral extent of the LOCOS bird's beak, non-planarity, thinning, and stress-induced silicon defects are addressed in their work. It is concluded that future CMOS technology will require an effective device isolation method that provides abrupt transitions to active device regions with a minimum impact on device characteristics or topography.
At 1996, S. E. Kim et al. disclosed a LOCOS technology in the work "Nitride Cladded Ploy-Si Spacer LOCOS (NCPSL) Isolation Technology for the 1 Giga Bit DRAM" (in IEDM Tech. Dig., p. 825, 1996). The limitation of the conventional LOCOS technology with the scaling down of the devices is illustrated. Fully recessed LOCOS is one solution to the problem. However, simply recessing the field regions before field oxidation brings about excessive bird's beak penetration. They merged the concept of RPSL (Recessed Poly-Si Spacer LOCOS) and RNSL (Recessed Nitride Spacer LOCOS) to reduce the bird's beak length while maintaining the smooth edge profile by employing selective SiN deposition on poly-Si spacer.
Although with better isolating characteristics than the LOCOS process, the trench isolation process is suffered from a large defects induced by dry etching and sharp trench corner effects. In the work of P. C. Fazan and V. K. Mathews ("A Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMs", in IEDM Tech. Dig., p. 57, 1993), the replacement of the LOCOS-based isolation schemes with the STI process is disclosed. STI provides a planar surface and a fully recessed field oxide, does not suffer from field oxide thinning, and can easily be scaled down for 1 to 4 Gb DRAM applications. However, STI also requires a much more complicated planarization procedure and carries the devices reverse narrow width effects. A trench isolation process combining tapered trench sidewalls, a trench reoxidation, a vertical B field implant, a CMP-only planarization, and disposable spacers to smooth the trench corners, is proposed in the work.
For solving the trench corner effects, a lot of methods and structures are developed. U.S. Pat. No. 5,521,422 to J. A. Mandelman is an example. In the work "Corner Protected Shallow Trench Isolation Device", a semiconductor structure to prevent gate wrap-around and corner parasitic leakage is proposed. A sidewall structure around the trench region is formed to solve the problems induced in the planarization process. The problems of the corner leakage and the recessed isolation insulator adjacent the corner is solved by the structure in their work with the additional sidewall structure.